A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI

摘要

This paper presents a very low-power 875 MS/s 7b single-channel high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a SNDR/SFDR at Nyquist rate of 41.46/55.01 dB. The use of an integer-based split CDAC combined with an improvement for the LSB capacitor allows a substantial improvement in the SNDR. A simple and accurate calibration procedure for the ADC is presented thanks to body biasing. The ADC is designed in 22 nm FDSOI while consuming 1.65 mW from a 0.8 V supply with a core chip area of 0.00074 mm^{2. The Walden figure-of-merit of 19.5 fJ/conversion-step at Nyquist rate making it one of the lowest among recently published medium resolution SAR ADCs.}