A fast selection algorithm based on binary numbers for capacitor voltage balance in modular multilevel converter

摘要

Considering the capacitor voltage balance (CVB) in modular multilevel converter (MMC), classical complete sorting algorithms, especially used in MMC with a large number of submodules (SMs), usually result in too much computational load and resource consumption. A fast selection algorithm based on binary numbers is proposed to achieve CVB in MMC. The algorithm needs not fully sorting all the numbers, and the complexity of it rapidly decreases by using a binary division mechanism. These properties make the proposed algorithm fast and resource-saving, and easily being implemented in many types of microcontrollers. Taking into account the needs of engineering applications, some techniques used to improve algorithm speed and reduce Filed Programmable Gate Array (FPGA) resource consumption are discussed when implementing algorithms in FPGA. The required resources and execution time of the proposed algorithm is evaluated, and a comparison between the proposed algorithm and some other sorting algorithms is used to verify the conclusions.