An Energy-Efficient Asymmetric Multi-Processor for HPC Virtualization

摘要

The Asymmetric Multiprocessor (AMP) architecture brings new opportunities to achieve better trade-offs between performance and operational/financial costs. This paper presents the case of an AMP to address poor I/O performance in a virtualized HPC system, by using small side-cores to offload I/O processing. We use full machine simulations to explore the micro-architectural parameter space in detail and perform an energy-delay-area analysis, taking into account the relationship between size and access delay in the caches. The simulation side-core model has been validated on the Atom processor, with performance counter metrics being within 11%. study focuses on TLBs and caches which our results show to have a remarkable impact on performance. Compared with a previous AMP study considering only performance and limited to existing hardware, our results confirm the broad nature of that design, including the preference for an asymmetric 2-way CPU pipeline. Our improved methodology also boosts the degree of confidence in these results. We however show that the optimal features of an efficient side-core are smaller and simpler L1/L2 caches (16KB 4-way and 16KB 2-way I/D caches and a 128KB 4-way L2 cache) and L1/L2 TLBs (32/48 entry fully associative L1 I/D LBs and 256 entry 4-way L2 I/D TLBs). Meanwhile, our analysis reveals that a processor module consisting of two big cores and a small side-core of our design can reduce average power, energy, and area by 9.2%, 8%, and 24.4%, respectively, compared with a module of three big cores (the AMD K10), while retaining performance (at the cost of 1.3% performance loss).