Static Timing Analysis of Asynchronous Bundled-Data Circuits

摘要

Self-timed circuits appear today as an attractive solution for designing robust and low-power chips dedicated to smart sensing and Internet of Things (IoT) platforms. However, a massive adoption of this technology by the industry requires industrial-grade tools for the whole design flow. The gap between asynchronous bundled-data and synchronous circuits is sufficiently tight to exploit the existing commercial tools without impacting the design flow and the time-to-market. This paper especially addresses the timing analysis of asynchronous bundled-data circuits with standard EDA tools and presents a method for exhaustively defining and verifying their relative timing constraints. This new approach only uses a combination of clocks to describe every possible event propagation path, allowing the tools to fully capture the relative timing constraints. Moreover, this can be adapted to different controller implementations and fully automated. A case-study, based on a 128-bit AES implemented in UMC 55nm uLP technology, illustrates the proposed methodology and evaluates its efficiency in terms of complexity and execution time.