Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter

摘要

This work presents a strategy for static linearity self-testing of successive-approximation analog to digital converters (SAR ADCs) with the goal of reducing test time. The proposed test technique takes advantage of the SAR ADC architecture to drastically reduce the number of necessary measurements for a complete static linearity characterization. Moreover, we show that static linearity measurements can be performed on-chip without the need of a test stimulus generator, by generating the major carrier transitions of the SAR ADC and acquiring them with a low resolution ADC. The proposed test circuitry is reduced to a simple incremental ∑Δ ADC. The technique is validated with behavioral simulations and the design trade-offs of the proposed test circuitry are explored.