As design complexity rapidly grows, a modem design contains more complex constraints and has more clock domains. To these stringent timing requirements, a design is iteratively optimized. Along with intensive optimizations, fast timing analysis guiding designers to fix timing violations is desired. Thus far, previous works have focused on either timing exception handling or path search only. Different from them, in this paper, we tackle these two issues together for the urgent need in modern design. We first generalize timing exceptions to model all common timing exceptions and other path-specific timing quantities. Then, we propose a novel timing analysis flow that performs fast path search for generalized timing exception handling. Furthermore, we develop three delicate techniques to achieve fast path search, including local slack bounds, dynamic slack recovering, and slack priority queue. Experimental results show that our model is general, and our flow is promising with high efficiency and scalability.
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