Autonomic Secure HPC Architecture Against Power Attacks

摘要

High Performance Computing (HPC) systems are enabling broad computing capabilities across scientific simulations, data analytics, and machine learning. Such HPC systems are composed of high-end compute elements (CPUs, accelerators, co-processors...) to handle high throughput and high parallelism, which results in significant power consumption. However, the power infrastructures built for such systems are proportionately older and may not be built to sustain system's peak power for extensive periods of time. Therefore, innovative power management schemes are used to allocate power across all system's components within a given power limit. HPC power management systems regulate resources' power within budget constraints and the overall system's power limit. Failing not to limit system's power consumption can result in operational failures that can bring down the whole system. Additionally, system reliability would be compromised under extensive computational system power and temperature. In addition to power consumption, possible attack scenarios can cause reliability issues where the attackers can manipulate the reported data of the measured power that is used for power management, which in turn can misguide the schedulers or can assign tasks that will result in exceeding the power limits, leading to system failures. Hence, intrusion detection systems (IDS) for power attacks are extremely important. This paper presents a framework for power attack IDS and describe each steps to be taken.