A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing

摘要

A hybrid Hardware Trojan detection technique is proposed in this paper that combines Combinatorial Testing in order to consistently trigger the Hardware Trojan, if one is present, and a grid of compact on-chip sensors in order to detect differentiations in the circuit of the FPGA. Each sensor mainly consist of a three stage Ring Oscillator and a compact Residue Number System ring counter and requires just two FPGA slices, leading to a total overhead of less than 2% in hardware resources. The proposed technique was tested on a cryptographic module performing AES cipher. To emulate the effects of a Hardware Trojan, we used a 64-bit Linear Feedback Shift Register. The experimental results prove that the proposed hybrid technique can detect the presence of a Hardware Trojan.