Design and Implementation of DDR3 SDRAM Controller

摘要

This paper implements the memory controller and its PHY layer on the FPGA according to the DDR3 timing requirements. Successive comparison algorithm this paper proposes and Digital Clock Manager(DCM) are used to realize fast and accurate write leveling and the final phase skew is within 39ps. This paper proposes loop access strategy for memory access, which reduces the waiting time and improves the actual data bandwidth. This design is implemented on XC4VSX55 FPGA chip of Xilinx. The experimental results show that the memory controller bandwidth is 9.1Gbps, and the interface bandwidth is 2.28Gbps.