A 0.032-mm2 Fully-Integrated Low-Power Phase-Locked Loop Based on Passive Dual-Path Loop Filter

摘要

This paper presents a low-power and area-efficient PLL-based frequency synthesizer. The area-saving technique is based on dual-path loop filter which involves no additional active components overhead and inductor-less ring voltage-controlled oscillator (VCO). In addition, digitally controlled duty cycle corrector (DCC) and locked detector (LD) both utilized to calibrate the duty cycle of output signals are introduced. To verify the feasibility of the proposed technique, a integer-N PLL is built in standard 180-nm CMOS technology, which can cover a wide range of frequency from 0.2 GHz to 2 GHz with average RMS jitter of 0.98 ps. It consumes 3.7 mA from 1.8-V power supply at 2 GHz output frequency and occupies an active area of only 0.032-mm².