A Harmonic Rejection Downconverter with a GHz PWM-Based LO

摘要

A harmonic rejection downconverter that employs a pulse-width modulated local oscillator (PWM-LO) signal is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with signal-path switches decreases the sensitivity of the harmonic rejection ratio (HRR) to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3^rd and 5^th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform.