Fault tolerant design for cascaded H-bridge multi-level converter based electronic power transformer

摘要

As a prospective electric component in the power grid, the reliability of electronic power transformer (EPT) affects the security of the power grid. The fault tolerant strategy about the redundancy control can improve the reliability of EPT, hence secure the power grid. This paper presents the design of fault tolerant strategy on a cascaded multi-level converter (CMLC) based EPT. The operational principle and control scheme for the redundancy control are introduced and analyzed. The proposed fault tolerant strategies are implemented on a single phase nine-level CMLC based EPT in Saber simulation platform. Simulation is illustrated to verify the performance of the proposed fault tolerant design with redundancy control.