Timing-critical path analysis with structurally synthesized BDDs

摘要

Timing-critical paths analysis is one of the key-important tasks in the field of design and test of digital circuits and systems. It has applications in time critical path identification, in path delay simulation, in gate-level reliability analysis. To cope with the complexity of the timing analysis of digital circuits at the logic level, we present in this paper a novel hierarchical approach to analysis. We propose to present the circuits at two levels - at the flat gate-level for modules or sub-circuits, and at the higher architectural level as a network of modules. The results of timing analysis carried out at the gate-level for modules are used for calculating the delays on the topological critical paths determined as paths through the network of higher level modules. To speed-up the module level timing analysis, the theory of Structurally Synthesized BDDs (SSBDD) is used. Experimental results demonstrate considerable speed-up of the SSBDD based timing analysis, compared to the flat gate-level analysis.