Probabilistic Analysis of Timing Constraints in Autonomous Automotive Systems Using Simulink Design Verifier

摘要

Modeling and analysis of timing constraints is crucial in automotive systems. East-adl is a domain specific architectural language dedicated to safety-critical automotive embedded system design. In most cases, a bounded number of violations of timing constraints in systems would not lead to system failures when the results of the violations are negligible, called Weakly-Hard (WH). We have previously specified East-adl timing constraints in Clock Constraint Specification Language (Ccsl) and transformed timed behaviors in Ccsl into formal models amenable to model checking. Previous work is extended in this paper by including support for probabilistic analysis of timing constraints in the context of WH: Probabilistic extension of Ccsl, called PrCcSL, is defined and the East-adl timing constraints with stochastic properties are specified in PrCcSL. The semantics of the extended constraints in PrCcSL is translated into Proof Objective Models that can be verified using Simulink Design Verifier. Furthermore, a set of mapping rules is proposed to facilitate guarantee of translation. Our approach is demonstrated on an autonomous traffic sign recognition vehicle case study.