Design of Ultralow-Voltage High Speed Flash ADC in 45nm CMOS Technology

摘要

Analog to Digital Converters has an indispensable part in todays digitized world as they are suitable for a large range of applications. Flash ADC is the fastest ADC available, but it's power consumption is very large. This paper aims at developing an ultralow-voltage design policy for high speed medium resolution flash ADCs to improve the energy efficiency. The power consumption of a digital system can be minimized by reducing the voltage supply, but only with the hike in the delay time. Here a voltage boosting based comparator with forward body biasing technique is used to develop a flash ADC operating at ultralow-voltage(ULV) area using 45nm CMOS technology. This method reduces the power consumption by keeping the delay time almost constant as the supply voltage reduced. Body-bias calibration technique is used for offset compensation. Here, as a prototype a 5-bit flash ADC operating at 0.4V is developed in Cadence Virtuoso 45nm technology. The power and delay analysis of this proposed comparator shows a reduction in power with a constant delay time when the supply voltage is reduced. The power-delay(PD) product of this comparator is lesser than the conventional ones. The Figure-of-Merit Delay(FD) product of the flash ADC also shows a fair reduction of 0.54 p J n S/c-s.