Twiddle factor complexity analysis of Radix-2 FFT algorithms for pipelined architectures

摘要

This paper presents analysis of fast Fourier transform (FFT) algorithms for pipelined architectures that can be generated by using binary tree representation. Those algorithms have different twiddle factors, however the butterfly operations remain same. Twiddle factor can be implemented by different techniques, which has different hardware cost. This analysis is based on twiddle factors hardware cost of each FFT algorithm. In results, we have shown the trade-off between the hardware components of twiddle factor for selected FFT algorithms.