A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator

摘要

A 16-bit non-binary SAR ADC with noise-tunable comparator for low power consumption is presented. A nonbinary-weighted capacitive DAC with redundancy is used in the ADC to suppress the impact of incomplete settling, capacitor mismatch and kickback from the comparator. A tri-level DAC that reduces switching power improves ADC's power efficiency. A dynamic comparator is designed to implement noise tunability so that the comparator noise level is controlled during conversion depending on the DAC redundancy range to save power consumption. The ADC performance is estimated in simulation with standard CMOS 0.18pm technology, which shows THD of -93.1 dB at Nyquist input while it consumes 32.92pW that results in 39.0 fJ/conv.-step FoM. 31.9 % power reduction is achieved by the proposed noise-tunable comparator.