Low-voltage low-power four-quadrant analog multiplier in current-mode

摘要

In this paper, a four-quadrant multiplier designed by squarer circuit and rectifier is presented. The circuit is evaluated using ELDO simulator in 0.18μm CMOS parameters. For input range of ±20μA and a power supply voltage of ±0.6V, the THD, the -3db bandwidth and the power consumption are 0.75%, 32.2MHz and 0.63mW, respectively.