Investigation of capacitor voltage balancing in practical implementations of flying capacitor multilevel converters

摘要

Flying capacitor multilevel (FCML) converters are known to naturally balance the capacitor voltages through the use of phase-shifted pulse-width modulation. However, in practice, the capacitor voltages can still deviate and active balancing is often required. This work investigates the origins of the voltage imbalance in practical implementations of such converters and presents corresponding solutions. It is shown that the source impedance and the input capacitor can have a drastic impact on the flying capacitor voltages. Moreover, we also demonstrate that an FCML converter with an even number of levels has significantly better immunity to the presence of source impedance than one with an odd number of levels. It is also found that gate signal propagation delay mismatch from half-bridge gate drivers will lead to capacitor imbalance. An alternative gate drive power supply circuit is designed to address this problem. Lastly, variations of switches' on-resistance are found to have a small impact on the capacitor voltage balance.