Data compression and decompression Integrated Circuit for AC Power Quality data

摘要

This paper presents the integration of a Power Quality (PQ) data compression/decompression Application Specific Integrated Circuit (ASIC) into an AC power quality analyzer. The integration of the ASIC improves substantially the system data storage capabilities. The paper describes the compression algorithms implemented in dedicated CMOS circuitry. Compression results obtained from real power line measurements are herein shown to prove the effectiveness of our compression/decompression ASIC. This chip has a die area of 15mm, more than 400k 2-input logic gates equivalent, and 10 SRAM modules, all integrated into a 180nm digital CMOS technology. To the best of our knowledge this is the first lossy compression/decompression ASIC design for registering power quality trends over time, which is also compliant with the IEC 61000-4-30 standard accuracy requirements, fully tested and functional in a Class A system hardware PQ analyzer.