An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array

摘要

Interconnection network plays an important role in Coarse-Grained Reconfigurable Arrays and it has a significant influence on the performance, area overhead and power consumption. To make the interconnection network adapt to the mapping of cryptographic algorithms with lower area overhead, an area-efficient interconnection network based on the Mesh topology structure is proposed, and a new kind of routing node is constructed. Based on the 55 nm CMOS standard cell library to design, the throughput of the interconnection network is 37.5 GB/s, and the area is 0.37 mm², which is 4.9% of the total area of the system. Compared with the related classes, the area ratio is decreased obviously; structure dynamic reconstruction rate is 5-150 times higher; and the utilization rate of the reconfigurable cryptographic processing blocks is also improved greatly.