Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme

摘要

A single-phase clocked redundant-transition-free flip-flop (SRFF) is proposed in this paper for achieving high power efficiency. A conditional charging scheme is utilized in the proposed SRFF to eliminate the redundant transitions at internal nodes when the input data and output are at the same logic levels in consecutive clock cycles. The long stacked transistor paths in the previously published FFs are also avoided in the new SRFF. The clock power consumption of the proposed SRFF is reduced by up to 81.99% as compared to the previously published flipflops with 40nm CMOS technology. Furthermore, the proposed SRFF provides up to 65.64% savings in dynamic power consumption while maintaining similar data-to-output delay as compared to the previously published flip-flops at a typical data switching activity of 20%.