Design and performance analysis of multipliers using Kogge Stone Adder

摘要

Adders are known to have being frequently used in VLSI designs. This work deals with the designing and implementing multipliers using the underlying principle of parallel prefix adders. We are looking for less delay specific multiplier, so among the prominent PPA's like Kogge Stone Adder(KSA), Sparse Kogge Stone Adder(SKSA), Brent Kung Adder(BKA) and Lander Fischer Adder(LFA), we choose to implement the fastest PPA, i.e., KSA to get a comparative idea about the performance of four different multipliers namely; Binary multiplier, Braun Multiplier, Yedic Multiplier and Baugh Wooley Multiplier. Further the synthesis and simulation results reveal better idea about the proposed multipliers by giving an in depth view of their area, delay and power. A brief discussion about the application of the above is done. We have used Cadence Software and TSMC 180 nm technology.