Performance analysis of CNTFET based low energy and low power adiabatic logic design

摘要

The adiabatic techniques are widely used to decrease energy dissipation in conventional CMOS circuits. This article presents performance analysis of CNTFET based low energy and low power adiabatic logic. This logic can be used to decrease the dissipation in PMOS network and to restore the energy available at load capacitance and to recycle it instead of dissipating heat. But adiabatic technique is highly based on the parameter variation. Using CADENCE simulations, the energy consumption and power dissipation is analyzed by a variety of parameter. The charge recovery of ECRL, PFAL and APFAL logics have simulated using Carbon Nano-Tube Field Effect Transistor (CNTFET). Due to fast switching properties of CNTFET, the dynamic power will be minimized and thus low leakage will be one of the key factors to reduce power. The CNTFET is the promising alternative over silicon due to ballistic transport and low OFF-current properties. Simulation results of CNTFET based adiabatic circuits have been simulated using Verilog-A model file in CADENCE simulator tool and proved its efficiency in terms of energy.