Gain and linearity trade-off in time-difference amplifier design

摘要

In this paper, the effect of the design parameters on an S-R latch time-difference amplifier (TDA) gain and dynamic range is presented. In the TDA design, an n-voltage-controlled delay element has been used instead of the cascaded inverter to control the gain of the TDA using dc voltage, and optimizing the XOR gate by six transistors implementation to achieve faster operation. The trade-off between the gain and the dynamic range of operation is discussed. TDA with different gain has been simulated in a 130 nm CMOS process using 1Gb/s as data rate. A maximum gain of 9.22 has been achieved with a dynamic range of 6 ps and a maximum dynamic range of 72 ps has been achieved with a gain of 2.05. The effect of the each design parameter on the gain and the dynamic range has been simulated.