Power and signal integrity design of TSV in 3D ring oscillator

摘要

The coupling between adjacent through-silicon vias (TSVs) in 3D IC has been designed and analyzed from the power and frequency view. At first presented 2D 13 stage ring oscillator which consists of 45nm VTH CMOS transistors. Then 3D ring oscillator has been explored which consists of 3 tiers, where each tier consists of 4 or 5 inverters and each tier connected to the next tier vertically by TSV. The frequency and power is measured for schemes and compared to each other to show the impact of TSV coupling.