In the nanometer era where the operating speed of a chip decides its price, design companies rely on high-qualty speed binning approaches to maxmizie their profits. The conventional speed binning approach is legacy (i.e. structural) since functional tests are too expensive to derive. Besides legacy and functional tests, recent studies tried to apply the notion of delay testing for deriving speed-binning patterns; however, all of them could not determine the number of patterns required for speed-binning nor taking process variation into consideration. Therefore, in this paper, we propose a speed-binning pattern generation (SBPG) method to deterministically generate a high-quality pattern set for speed binning. This SBPG mainly consists of two core techniques: (1) empirical variation sampling (EVS) and (2) functional timing analysis (FTA), which efficiently derives few high-quality patterns from a small number of learning samples. SBPG achieves a satisfactory accuracy (> 99% on average) for five benchmark circuits under various conditions of process variation, and is shown to be an efficient solution for speed binning.
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