Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker

摘要

In this paper a verification architecture called Multi-Processor Memory Scoreboard (also referred as MPMS, the checker, the scoreboard in this paper) developed at Samsung Austin Research & Development Center is described. This is a RTL simulation based scoreboard which performs data consistency and memory ordering checks as required by ARMv8 ISA memory model and finds RTL errors very close to the failure point. Along with the knowledge of architectural memory ordering requirements, the scoreboard employs age-order and time-order relations of instructions of the test programs and performs data consistency and memory ordering checks.