Design and simulation of steep-slope silicon-on-insulator FETs using negative capacitance: Impact of buried oxide thickness and remnant polarization

摘要

This paper discusses the importance of determining a suitable value of the buried oxide (BOX) thickness and remnant polarization in ferroelectric silicon-on-insulator FETs to attain a steep subthreshold swing (SS) by exploiting the negative capacitance effects. We reveal that a small value of remnant polarization Pr (3 μC/cm2 at most) and ultrathin BOX (<; 10 nm) are key to realizing SS <; 60 mV/decade.