A study on the effect of test vector randomness on test length and its fault coverage

摘要

This paper presents a study on the impact of test sequence randomness and the fault coverage (FC) it could produce through the use of a modified structure of the conventional linear feedback shift register (LFSR). By using double input signals, the modified LFSR can control the number of test patterns generated and also prevents the sequences from being stuck in all zeroes state. Fault simulations on ISCAS'85 benchmark circuits show that a high FC for combinational logic circuits has been obtained. Another observation is that the modified structure could achieve high FC with a smaller test sequence compared to other reported test pattern generation (TPG) techniques.