A low power 0.18μm CMOS technology integrating dual-slope analog-to digital converter

摘要

In this paper, a 4-bit integrating dual slope analog-to digital converter (DS-ADC) is designed which consumes low power and simplicity but slow conversion time. The design utilizing a Silvaco Electronic Design Automation (SEDA) tools with an advanced 0.18μm CMOS Technology using 1.8V power supply. This integrating dual slope ADC contains five main components, which are switching, integrator, comparator, control logic and counter at which the integrator is realized with a two-stage operational amplifier (op-amp) that provides sufficient gain, ICMR and low power dissipation. Simulation confirms that the proposed DS-ADC architecture shows a power efficiency of 2.4739mW with 1.06μs conversion time.