ECP technique based capacitor-less LDO with high PSRR at low frequencies, ?89dB PSRR at 1MHz and enhanced transient response

摘要

An external capacitor-less low dropout (LDO) voltage regulator with high PSRR and enhanced transient response is presented. The novel idea is applying a replica circuit which can pull excessive current. Excessive Current Pulling (ECP) technique decreases the equivalent output impedance to enhance transient response. The proposed LDO has been simulated in 0.18 μm CMOS Technology. Its regulated output voltage is 1.6 V with the power supply of 1.8 V. The proposed technique has the advantages of simulated PSRR of -88.7 dB at 1 MHz and -67 dB at 100 KHz. Overshoots and undershoots are less than 45.2 mV and 30 mV under the load varies from 50 mA to 0 mA with rise/fall time of 100ns, respectively. Simulation results show that the achieved line regulation is 28.3 mV/V and the load regulation is 0.33 %/mA.