Fault injection attacks have become a serious threat against cryptographic ICs. The existing countermeasures rely on error detection and correction, which brings a large area and power overhead. This paper proposes a security enhancement design method against fault injection attacks, which selectively protects or detects only the vulnerable logic cells in a cryptographic circuit. These vulnerable cells of the cryptographic ICs can be accurately identified on the system level and the security enhancement will be conducted only on these cells on the circuit level. This security enhancement design method has the advantages of smaller area and power overheads, transparency to the IC designers and compatibility to the common electronic design automation (EDA) tools.
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