首页> 外文会议>IEEE International Conference on Anti-counterfeiting, Security, and Identification >Parallel mapping implementation of AES for Coarse-Grained Reconfigurable Block Encryption Array
【24h】

Parallel mapping implementation of AES for Coarse-Grained Reconfigurable Block Encryption Array

机译:粗粒度可重配置块加密阵列的AES并行映射实现

获取原文

摘要

In this paper, we explore different parallel mapping implementations of Advanced Encryption Standard (AES) on the Coarse-Grained Reconfigurable Block Encryption Array(RBEA). To improve performance and resource efficiency of the direct mapping implementation, we propose 8 modified implementations based on merger, task duplication and loop unrolling methods. Experimental results show that the improved implementations increase the throughput from 1023.99 Mbps to 13643.96 Mbps and the performance-area ratio from 63.99 Mbps/FB to 309.62 Mbps/FB, developing the superiority of array's computing resources. Compared with other platforms, our work has 1.16–13.34 times higher throughput and 3.55–11.73 times higher throughput per unit of array area.
机译:在本文中,我们探索了粗粒度可重配置块加密阵列(RBEA)上高级加密标准(AES)的不同并行映射实现。为了提高直接映射实现的性能和资源效率,我们提出了8种基于合并,任务复制和循环展开方法的改进实现。实验结果表明,改进后的实现将吞吐量从1023.99 Mbps增加到13643.96 Mbps,性能/面积比从63.99 Mbps / FB增加到309.62 Mbps / FB,从而开发了阵列计算资源的优势。与其他平台相比,我们的工作量使每单位阵列面积的吞吐量提高了1.16–13.34倍,是3.55–11.73倍。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号