An efficient power multiple valued look up table for adder circuit using quaternary FPGA

摘要

VLSI technology is used for designing, verifying, fabricating and testing a chip. In look up table (LUT) system, the more interconnections are increasingly the dominant contributor to delay, area, and energy consumption in CMOS digital circuits. In existing system would require four QLUTs to properly implement this function, two QLUTs for each output, that is sum and carry out, working with the two possible values of the carry in. This method will have signal propagation delay and hence its decrease the speed of the circuit and more power is consumed. In order to overcome this problem multiple-valued logic is used, it can decrease the average power required for level transitions and reduces the number of required interconnections and also reducing the impact of interconnections on overall energy consumption. In proposed scheme, a quaternary look up table structure is designed to replace or complement binary LUT in FPGA. The proposed design include full adder is constructed using 16:1 multiplexer which overcome the limitations of existing method. The design will be synthesized using Modelsim 6.0 and Xilinx 14.2.