Reversible full/half adder with optimum power dissipation

摘要

In digital circuits power dissipation can be significantly reduced using reversible logic. It is becoming prominent in applications involving quantum computing and low-power design. A new reversible full/half adder using combination of Feynman (CNOT), Toffoli (CCNOT) and Fredkin (CSWAP) gates is proposed. The proposed reversible full/half adder is found to be efficient in reducing constant inputs (ancilla bits), garbage outputs, number of transistors and gate count. The proposed full adder shows 47% reduction in power dissipation, 33% in constant inputs, 50% in garbage outputs and 67% in number of transistors in comparison with similar work present in literature. The energy saving factor of the proposed full-adder is found to be 2.01.