Design of PLL based on FPGA under unbalanced conditions

摘要

This paper proposes a new way based on FPGA to realize decoupled double synchronous reference frame software phase locked loop (DDSRF-SPLL) under unbalanced conditions. DDSRF-SPLL can lock in unbalanced grid voltage accurately as well as overcome the impact of the phase-locked loop on frequency performance in adopting the positive and negative sequence decoupling algorithm. When the frequency of three-phase voltage under unbalanced conditions fluctuates, the frequency will be fed back to the AD sampling module through the PI regulator. Thus the sampling period is adjusted and the accuracy of phase-locked loop is improved. Simulation by ModelSim shows that the proposed three-phase PLL has strong anti-interference ability and good adaptability to frequency fluctuations.