Review of Parasitic Minimization Techniques for High Frequency Power Conversion

摘要

With significant advancements in traditional power semiconductor technologies and more recently the introduction of wide bandgap GaN power devices, power semiconductors switching capability has increased considerably in recent years. To fully utilize the ever-increasing performance offered by improved power semiconductors, packaging and printed circuit board layout techniques have been developed to minimize parasitic impact on semiconductor performance. This paper will provide a review of the advancements in power semiconductor packaging and printed circuit board layout techniques and conclude with potential parasitic minimization approaches of the future.