Design of an all-digital, low power time-to-digital converter in 0.18μm CMOS

摘要

A full custom, all digital, low power Time-to-Digital Converter (TDC) is proposed. The proposed architecture contains a 20-bit ripple counter, an encoder, an edge detector and a Ring Delay Line (RDL). The TDC core, has an active area of 0.026mm^{2implemented in 0.18μm CMOS technology that achieves a resolution of 586.4ps/LSB and 201.8ps/LSB, lower power consumption of 32.5μW and 315.5μW, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively, making it feasible for time-of-flight measurement in space applications.}