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Bit-parallel multipliers for different irreducible polynomials in finite fields

机译:有限域中不同不可约多项式的位并行乘法器

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Multiplications in finite fields are crucial due to the fact that they are widely used in areas of cryptography. We propose bit-parallel multipliers in finite fields for trinomials, Equally-Spaced-Polynomials (ESPs), pentanomials, All-One-Polynomials (AOPs), and Successive-One-Polynomials (SOPs). Main improvements of this paper with known results are as follows. First, SOP is first studied for finite field multiplication, which represents a polynomial with successive one. Second, we firstly propose multiplications for different pentanomials. We analyze our design theoretically and its executing time and area usage are given. Our design is well suited for Field Programmable Logic Arrays (FPGAs). We back up the claims with implementations of our design on Altera FPGAs.
机译:由于有限域中的乘法已广泛用于密码学领域,因此至关重要。我们在有限域中为三项式,等距多项式(ESP),五项式,全一多项式(AOP)和连续一项多项式(SOP)提出位并行乘法器。本文的主要改进如下:首先,首先研究SOP的有限域乘法,它表示具有一个连续多项式的多项式。其次,我们首先提出针对不同五项式的乘法。我们从理论上分析了我们的设计,并给出了其执行时间和面积使用情况。我们的设计非常适合现场可编程逻辑阵列(FPGA)。我们通过在Altera FPGA上实现设计来支持这些主张。

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