Reducing DRAM Cache Access in cache miss via an effective predictor

摘要

As more and more cores are integrated on a single chip, memory speed has become a major performance bottleneck. The widening latency gap between high speed cores and main memory has led to the evolution of multi-level caches and using DRAM as the Last-Level-Cache (LLC). The main problem of employing DRAM cache is their high tag lookup latency. If DRAM cache misses, the latency of memory access will be increased comparing with the system without DRAM cache. To solve this problem, we propose an effective predictor to Reduce DRAM Cache Access (RCA) in cache miss. The predictor composes of a saturating counter and a Partial MissMap (P_Map). If the saturating counter indicates a hit, then the request will be send to the P_Map to further lookup whether it is a hit or not. The evaluation results show that RCA can improve system performance by 8.2% and 3.4% on average, compared to MissMap and MAP_G, respectively.