A Cache Design Assessment Approach for Embedded Real-Time Systems Based on Execution Time Measurement

摘要

Due to the increasing complexity of embedded systems, simulation is of paramount importance during design phase. Often such systems must obey real-time constraints, calling for worst-case execution time assessment mechanisms. Although there is a wide range of simulation tools in the embedded systems domain, mechanisms for performing high abstraction level estimates for task execution times within a controlled environment are still needed. Non-determinism introduced by cache, multi-core and operating systems, for example, makes timing analysis highly complex or even impossible. We address this problem by presenting a RISC-V Instruction Set Simulation platform equipped with a task profiling mechanism for cache aware execution time measurements. The generated SystemC processor simulation model is integrated within a high abstraction level simulation platform with main memory and cache. Experimental results show that by making use of this kind of platform, designers can easily monitor task execution time as a function of measured code portion, cache sizes or cache policies employed helping in their decisions.