Design of a low-power RNS-enhanced arithmetic unit

摘要

In this paper, we propose a new approach to use Residue Number System (RNS) to design an arithmetic coprocessing unit, which allows to parallelize execution of addition and multiplication. The chosen RNS is a 5-moduli set composed of a larger even modulus 213 and four moduli of the type 2n ??? 1, which all fit into the 32-bit word of the processor. The RNS operations are implemented in hardware, except for the reverse conversion which is implemented in software. Simulation experiments performed on synthesized five-operation arithmetic unit show that at a small hardware and software cost can be achieved 10% energy saving for a constant-coefficient filter application and up to 25% for the matrix multiplication, compared to executions using a positional arithmetic unit.