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A simulation technique to test on board software — EEPROM hardware interface using SILS facility

机译:一种使用SILS设施测试软件软件测试的仿真技术 - EEPROM硬件界面

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ISRO Satellite Centre (ISAC) is the lead centre for development and operationalisation of communication, remote sensing and interplanetary missions. These satellites contain highly advanced embedded systems carrying out critical operations thus achieving mission goals. In the ISRO's current generation of spacecrafts, as autonomy taking the centre stage, complexity of spacecrafts have increased manifold. Attitude and Orbit Control Electronics (AOCE), is one of the main subsystems where most of the autonomy features are implemented. To handle autonomy functionalities, Electrically Erasable and Programmable Read Only Memory Management (EEPROM) is interfaced with AOCE On board software. On-board autonomy functions use data and logics stored in EEPROM memory via onboard software. Testing these interface logics had an inherent constraint in performing number of write operations on EEPROM device[1]. Overcoming this limitation and performing exhaustive testing of autonomy and EEPROM interface logics was a challenge. Simulation based test facility was already established to test all on-board software functionalities. Hence, EEPROM memory device had to be simulated and interfaced with this test facility, in order to test on-board autonomy functions. In addition, along with EEPROM, other memory devices like, Storage Random Access Memory (RAM) and Programmable Read Only Memory (PROM) are used for various critical functionalities. Having a device specific simulation model for EEPROM, Storage RAM and Programmable Read Only Memory (PROM) although technically feasible, lacks software reusability, thereby increasing development and testing time. To make the memory controller simulation more generic and reusable object oriented methodology was used [2]. The design model described in the rest of the paper provides an overview of the same. This paper focuses, mainly on the design methodology used to simulate EEPROM as a case study. This paper also discusses in brief the results obtained by testing using this simulation technique and advantages reaped from the same.
机译:ISRO卫星中心(ISAC)是沟通,遥感和行星任务的开发和运作领先中心。这些卫星含有高度先进的嵌入式系统,旨在实现关键操作,从而实现任务目标。在ISRO当前的航天器中,作为自治的临时阶段,航天器的复杂性具有增加的歧管。态度和轨道控制电子(AOCE)是主要的子系统之一,其中大多数自治功能都是实现的。为了处理自主功能,电擦除和可编程只读内存管理(EEPROM)与船上软件上的AOCE接口。板载自主函数通过板载软件使用数据和逻辑存储在EEPROM内存中。测试这些接口逻辑对EEPROM设备的写入操作数进行了固有的约束[1]。克服这种限制和执行对自主权和EEPROM接口逻辑的详尽测试是一项挑战。已建立基于仿真的测试设施以测试所有车载软件功能。因此,必须使用该测试设施模拟和接地,以便对板载自主功能进行模拟和接口EEPROM存储器。另外,与EEPROM一起,其他存储器设备如,存储随机存取存储器(RAM)和可编程只读存储器(PROM)用于各种关键功能。具有用于EEPROM的设备特定模拟模型,存储RAM和可编程只读存储器(PROM)虽然技术上可行,但缺乏软件可重用性,从而增加了开发和测试时间。为了使内存控制器仿真更加通用和可重复使用的面向对象的方法[2]。本文其余部分描述的设计模型提供了相同的概述。本文主要侧重于用于模拟EEPROM作为案例研究的设计方法。本文还简要讨论了通过使用该仿真技术进行测试获得的结果,并从中获得的优点。

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