Gate Diffusion Input-Based Design for Carry Select Adder

摘要

The regular carry select adder (CSLA) is designed using RCA-RCA configuration. It uses two individual RCA with different anticipated carry input values (C_(in) = 0 and C_(in) =1). After the calculation, the appropriate sum and carry-out will be selected using a multiplexer depending on the logic state of the carry input. In recent times, several architectures in CSLA adder were proposed. Boolean to Excess-1 converter (BEC) was one among them. This BEC-1 converter will be used instead of RCA with C_(in) = 1, such that the CPD can be reduced. The alternate approach was using common Boolean logic (CBL). This method also succeeded in reducing the CPD. Apart from these two architectures of CSLA, the proposed architecture in this chapter has shown a significant amount of results on reducing the CPD of the binary adder. In this chapter, the proposed CSLA adder employs single stage scheme such that the logic burden can be reduced. In this single stage architecture, the partial sum will be generated for the given input data, later the carry selection will perform according to the input carry then followed by the full sum generation. Thus, it has a single stage carry selection process. In this chapter, the sum generator uses A GDI-based XOR gate. Full Adder (FA) which was used to perform the sum generation was replaced by GDI Full Adder which is an efficient low power adder. Thus, the proposed adder will adopt high speed, low area, and power efficient adder. The comparison results were also discussed in the results section.