Design, implementation and analysis of power efficient polyphase multirate filters

摘要

Multirate filtering technique is widely used for meeting the sampling rates of different systems and it is a powerful technique in DSP which results in low-cost implementations of digital filters. Polyphase decomposition technique reduces the computational complexity by adopting parallelism in multirate digital filters. Power consumption is always a prime design constraint while implementing multirate digital filters on reconfigurable hardware. Dynamic power consumption in digital implementations can be reduced by minimizing the switching activity at the output of CMOS gates. Most of the work is revolved around minimizing number of power of two or nonzero terms in the filter coefficients as each non-zero bit corresponds to an additional adder in hardware implementation. This paper proposes a novel algorithm to reduce the switching activity at the output of CMOS gate by reducing the number of nonzero terms in the filter coefficients. The proposed algorithm is applied to the polyphase structures and its impact on dynamic power consumption is analyzed. The structures are synthesized for Spartan6 FPGA board using Xilinx System Generator. The proposed algorithm reduces the power consumption up to 31 milli Watts for the polyphase structures.