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A high gain down-conversion mixer in 0.18um CMOS technology for ultra wideband applications

机译:采用0.18um CMOS技术的高增益下变频混频器,用于超宽带应用

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In this paper, a high gain as well as highly linear down-conversion mixer is presented for UWB applications. The proposed mixer circuit is implemented and simulated in a 0.18μm CMOS technology using Advanced Design System (ADS) software. The core of the proposed mixer is based on the Gilbert cell (double-balanced) mixer with source degeneration (inductive) at the RF driver stage and the inductors between the RF (or driver) stage and the LO (or switching) stage. An LC type impedance matching network is employed at the RF port to minimize reflections at RF port. The mixer circuit is designed for a RF frequency of 3.35 GHz, LO frequency of 3.60 GHz, and IF frequency of 250 MHz. The proposed mixer circuit achieves a conversion gain of 11.679 dB, an IIP3 of -1.536 dBm, 1dB compression point of -12.764 dBm and a single sideband noise figure of 5.460 dB while operating at a DC supply of 1.8V.
机译:本文针对UWB应用提出了一种高增益以及高度线性的下变频混频器。使用高级设计系统(ADS)软件在0.18μmCMOS技术中实现和仿真提出的混频器电路。拟议的混频器的核心基于吉尔伯特单元(双平衡)混频器,在射频驱动器级具有源极退化(电感性),在射频(或驱动器)级与本振(或开关)级之间具有电感器。在RF端口处使用LC型阻抗匹配网络,以最大程度地减少RF端口处的反射。混频器电路设计用于3.35 GHz的RF频率,3.60 GHz的LO频率和250 MHz的IF频率。拟议的混频器电路在1.8V直流电源下工作时,可实现11.679 dB的转换增益,-1.53​​6 dBm的IIP3,-12.764 dBm的1dB压缩点和5.460 dB的单边带噪声系数。

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