Internet; Internet of Things; field programmable gate arrays; random-access storage; transceivers; FPGA; GTL; GTLP_DCI; I3 operating frequency; I5 operating frequency; I7 operating frequency; IO standard; IP address; Internet of Things; IoT; Moto-E operating frequency; Moto-X operating frequency; RAM design; energy efficiency; frequency 3.6 GHz; gunning transceiver logic; gunning transceiver logic plus; size 65 nm; word length 128 bit; Clocks; Energy efficiency; Field programmable gate arrays; Internet of things; Power dissipation; Random access memory; Standards; Energy Efficient Design; FPGA; GTL Thermal Aware Design; GTLP; Internet of Things; RAM;
机译:应用特定的缓存设计使用基于STT-RAM的基于FPGA的软处理器的块RAM
机译:基于闪存的FPGA中BRAM的不同ECC缓解设计的实现和验证
机译:基于XSG的HLS流程可为FPGA优化信号处理设计
机译:基于GTL基础的Internet互联网使处理器特定的RAM设计在65nm FPGA上
机译:用于诊断和修复基于FPGA的设备的基于Internet的技术。
机译:基于FPGA的电子皮肤实现实时数字信号处理
机译:基于FpGa的图像和视频处理系统的特定领域设计工具