A Methodology to Build Models and Predict Performance-Power in CMPs

摘要

Data centers have time-varying traffic and a wide range of demands in performance-power for the workloads. Understanding the trade-offs between performance and power for these varying types of demands given the time-variations, helps administrators to control the total power consumption and also facilitate for enhancing Quality of Service (QoS) levels. In this paper, we provide a methodology for administrators to predict performance and power using performance monitoring counters at all processor frequency states (P-States) and across a wide range of processor sleep intervals (Cl-States). This methodology will allow administrators to make quick decisions. Specifically, we build models and validate them using SPECcpu2006 benchmarks on an Intel Sandy Bridge processor with 4 cores, 9 P-States and 50 Cl-States resulting in a total of 40 billion configurations when running 4 threads in parallel. The modeling technique provided is fast (under 60,000 cycles), and requires a small period of time to build (less than 10 hours). The modeling technique predicts with a high accuracy and the results obtained show an average error in prediction of 2.25% and 13.99% (with a 95% confidence interval) for power and performance, respectively. Moreover, we provide an insight into the usability of these models in multi-core architectures by predicting performance and power for 3 different types of workloads under 9 different types of QoS constraints. The results obtained show an error in prediction of 9.02% and 7.45% (with a 95% confidence interval) for the total energy and performance delay respectively in multi-core architectures.