Energy-efficient, Delay-aware packet scheduling in high-speed networks

摘要

In current commercial routers, increased execution speeds of Network Processor Units (NPUs) in Line Cards (LCs) significantly improve network QoS performance. Achieving high network performance, however, may come at a high cost of routers' energy consumption. Dynamic Voltage Frequency Scaling (DVFS) and Dynamic Power Management (DPM) have been proposed as schemes to manage power and reduce energy consumption. Excessive reduction in execution rates or extended sleep periods to save energy, however, could result in severe network degradation which in turn may lead to violation of QoS requirements of the underlying applications. To address the energy-QoS dichotomy, we propose a congestion- and energy-aware packet scheduling scheme to achieve a balance between network delay and energy saving. The scheme, referred to as Queue Length (QL)-based Delay-aware packet scheduler (QLDA), uses multiple queue length thresholds to accurately capture network congestion. In response to different levels of network congestion, the QLDA scheme uses carefully designed frequency adjustment strategies to control execution rates in line cards and achieve high energy savings, without violating the delay requirements of the underlying applications. The simulation results show that the QLDA scheme has potential for significant energy saving in high-speed networks. Furthermore, a simulation study is carried out to compare the performance of the proposed scheme to other DVFS-based schemes described in the literature. The results show that the QLDA scheme outperforms the existing schemes for different network topologies and traffic loads, while meeting the delay performance of the supported applications.